） 摘要： 综述文章：本论文设计了一款适合音频应用的低功耗、高线性度ΣΔ ADC
孙颖等
65纳米工艺下低功耗高线性度音频ΣΔ 模数转换器的研究与实现[EB/OL]
北京：中国科技论文在线
主要研究方向为数模混合集成电路设计 通信联系人： 韩雁（1959
02- ） 浙江大学微电子与光电子研究所教授、博导
此 ADC包含了高性能2-1级联单比特量化ΣΔ 调制器和采用ROM、RAM设计的低功耗
同时实现了高性能与低功耗
本文设计的ΣΔ ADC在 22
05 kHz的音频带宽内
） Abstract： We designed an audio ΣΔ ADC which has low power consumption and high linearity
The proposed ΣΔ ADC contains a 2-1 cascaded 1- bit ΣΔ modulator and a low-power, area-efficient digital decimation filter which is designed using RAM and ROM
This chip has been implemented in SMIC 65nm mixed-signal 1P8M CMOS standard silicon process, and the die area is 0
581 mm2
Experiment results shown that 90 dB signal to noise plus distortion ratio (SNDR) and 93 dB dynamic range (DR) are achieved within 22
05 kHz audio band, at 5 M Hz sample rate
The ADC's power dissipation is 2
2 mW under 1
2 V supply voltage, which means that this chip obtains high-performance and low-power at the same time
Keywords： sigma-delta ADC; low-power; high-linearity; audio applications 下载PDF阅读器 PDF全文下载： 初稿 （ 154 ） 作者简介： 曹天霖 （1988
