FPGA模块设计使用Verilog HDL语言
） 摘要： 设计了以FPGA为核心逻辑控制模块的高速数据采集系统
FPGA is divided into some functional modules．The designing method and controlling flow of each module are discussed in detail．The Verilog HDL language is adopted in the FPGA module．Software design and system simulation are completed in the integration circumstance of Quartus Ⅱ 4
0．The paper provides the simulation figures of some FPGA modules．The system can acquire 16 bit analog signals with 200 kHz of maximal frequency signals
Keywords： FPGA; A/D; data acquisition; Verilog language 下载PDF阅读器 PDF全文下载： 初稿 （ 575 ） 作者简介： 通信联系人： 【收录情况】 中国科技论文在线： 施鸣鸣
基于FPGA的数据采集器的设计[EB/OL]
